This application claims the priority benefit of Taiwan application serial no. 90129017, filed Nov. 23, 2001.
1. Field of Invention
The present invention relates to a method of fabricating a read-only memory (ROM). More particularly, the present invention relates to a method of fabricating a mask ROM.
2. Description of Related Art
Since the read-only memory (ROM) has a non-volatile nature in data storage as the power is turned off, it has been used in a lot of electronic devices to provide the data necessary for the operation. The simplest read-only memory is namely the mask ROM, in which a memory cell is composed of a MOS transistor. The coding process of the mask ROM is done by implanting ions into the selected channel regions of the MOS transistors so as to change their threshold voltages, which in turn determine the switching state (On/Off) of each memory cell.
In a mask ROM device, there is a plurality of polysilicon word-lines crossing over a plurality of buried bit-lines, while a region under a word-line and between two bit-lines serves as the channel region of a memory cell. The value of the binary data (0/1) stored in one memory cell is determined by existence/absence of the implanted dopants in it, while the process of implanting dopants into the selected channel regions is called the coding implantation process.
FIG. 1 shows the schematic top view of a conventional mask ROM. As shown in FIG. 1, there are parallel word-lines 102 crossing over parallel bit-lines 104 and the coding process is performed by implanting ions into the selected coding region 110 to change the threshold voltage of the memory cell and control the switching state of the memory cell thereby.
Refer to FIG. 2, FIG. 2 schematically illustrates the coding process of a conventional mask ROM. As shown in FIG. 2, there are gate structures 206 on the substrate 200, buried bit-lines 208 in the substrate 200 between the gate structures 206, and a dielectric layer 210 covering the gate structures 206, wherein each gate structure 206 comprises a gate dielectric layer 202 and a gate conductive layer 204. In the coding process of this mask ROM, a patterned photo-resist layer 212 exposing a part of the gate structures 206 is formed with a photo-mask, then an coding implantation is performed to implant ions into the selected coding regions, i.e., the substrate 200 under the exposed gate structures 206.
However, in the conventional mask ROM mentioned above, each memory cell allows one-bit of storage only. Therefore, the integration of the mask ROM device cannot be easily increased if a larger memory space is required. Besides, an increase of the integration of the conventional mask ROM is also restricted directly by the development of the current manufacturing techniques.
Accordingly, a method of fabricating a mask ROM is provided in this invention, wherein each memory cell allows a two-bit storage so as to increase the integration of the device with the current manufacturing techniques.
This invention also provides a method of fabricating a mask ROM, in which larger coding windows can be formed to increase the margin of the coding process.
This invention further provides a method of fabricating a mask ROM, in which the buried bit-line can be formed with a shallower junction to prevent the leakage current, while the resistance of the bit-line can also be lowered.
According to the above-mentioned objects and others, in the method of fabricating a mask ROM provided in this invention, conductive strips are formed on the substrate with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips. The regions of the substrate under the first spacers located at one side of the conductive strips are taken as first coding regions, while the regions under the second spacers located at another side of the conductive strips are taken as second coding regions. Afterward, buried bit-lines are formed in the substrate between pairs of the first and the second spacers. A first coding mask is then formed over the substrate to expose a part of the first coding regions, then a first tilt coding implantation is performed to dope the exposed first coding regions. A second coding mask is formed to expose a part of the second coding regions after the first coding mask is removed, then a second tilt coding implantation is performed to dope the exposed second coding regions. The second coding mask and the cap layer are removed and a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and a plurality of gates, respectively.
One key point of the mask ROM disclosed in this invention is that a distance exists between a gate and one of the two adjacent buried bit-lines, and the region between the gate and the one buried bit-line is considered as a coding region. Therefore, two bits can be stored in one memory cell.
In addition, two tilt coding implantation steps are conducted in this invention to dope a part of the first coding regions and a part of the second coding regions, respectively, wherein the implanted dopants have the same conductivity type as that of the buried bit-line.
Besides, an additional raised polysilicon bit-line in this invention can be formed on each buried bit-line to form a bit-line with a lower resistance.
Additionally, since each memory cell allows a two-bit storage in this invention, it is feasible to miniaturize the device and to increase the integration of the device with the current manufacturing techniques.
Furthermore, since in this invention the coding mask as well as the conductive strips are used as the mask during the tilt coding implantation process, the width of the coding window can be increased so as to increase the margin of the coding process.
Moreover, since an additional raised polysilicon bit-line can be formed on each buried bit-line, it""s feasible to form a buried bit-line with a shallower junction in order to prevent the leakage current, meanwhile, the resistance of the bit-line can be lowered to improve the performance of the device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.